Process for oxide fabrication using oxidation steps below and above a threshold temperature

ABSTRACT

A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/597,076, entitled “PROCESS FOR FABRICATING OXIDES”, filed onJun. 20, 2000. The above-listed application is commonly assigned withthe present invention and is incorporated herein by reference as ifreproduced herein in its entirety.

TECHNICAL FIELD OF THE INVENTION

[0002] This present application relates to integrated circuitfabrication and particularly to a technique for fabricating a highquality, planar and substantially stress-free oxide.

BACKGROUND OF THE INVENTION

[0003] As integrated circuit (IC) complexity increases, the size ofdevices within the IC must decrease. To decrease the size of a device,the various elements of a device must be reduced proportionately. Thisis known as device sealing. In one type of device, ametal-oxide-semiconductor (MOS) structure, device scaling requires thatthe oxide layer be made thinner. Unfortunately, as conventional oxidesare made thinner (scaled), their quality tends to degrade. Thedegradation in oxide quality tends to adversely impact the reliabilityof a device using the oxide.

[0004] In addition to oxide quality, the reliability of the dielectricmaterial in a MOS structure may be affected by oxide stress and theplanarity of the oxide-substrate interface. Oxide stress can result fromlattice mismatch and growth induced stress. Lattice mismatch isdifficult to overcome and growth stress has been addressed in a varietyof ways with mixed results. Stress in the oxide may lead to dislocationsand defects especially in the interfacial region. This may result inmass transport paths and leakage current.

[0005] The reliability of a device is characterized by a fewconventional criteria. For example, in a MOS transistor reliability maybe characterized in terms of the change in conventional deviceparameters over time (known as device parameter drift). Additionally,time-dependent dielectric breakdown (TDDB) may be used to characterizereliability of transistor.

[0006] Under operating bias (applied voltage) and temperatureconditions, device parameters such as threshold voltage (V₁), saturationcurrent (I_(DSAT)) and transconductance (g_(m)) tend to drift tounacceptable values. In fact, the drift in device parameters duringnormal operation is thought to be more problematic than other knownreliability problems, such as dielectric breakdown of the oxide.Accordingly, in some cases, device parameter drift can cause a device tofail well before dielectric breakdown occurs.

[0007] In order to address the reliability issues discussed above, avariety of approaches have been tried. For example, it is known that thebest oxides for many IC devices are grown rather than deposited oxides.Furthermore, the higher growth temperatures may yield a better qualityoxide. Unfortunately, there are problems associated with fabricatingoxides at high temperatures by conventional techniques. For example, inachieving the high temperatures required in the high temperature oxidegrowth sequence, the overall thickness of the oxide grown tends toincrease. As a result the oxide may be too thick for a reduced dimensiondevice. Thus, in the effort to fabricate a better equality oxide, devicescaling objectives may be defeated. Moreover, when cooling down from thehigh growth temperatures, the viscosity of the grown oxide increases andgrowth induced stress may result. Given these issues, it is customary inthe semiconductor industry to grow oxides at low temperatures. Thedrawback to this practice is that by growing oxide at lowertemperatures, the oxide quality may be compromised. This reduction inquality adversely impacts reliability of the oxide for reasons discussedabove.

[0008] What is needed, therefore, is a process for fabricatingultra-thin oxides which overcomes the problems described above.

SUMMARY OF THE INVENTION

[0009] The present invention relates to a process for fabricating anoxide. A first oxide portion is formed over a substrate at a firsttemperature below a threshold temperature. A second oxide portion isformed under the first oxide portion at a temperature above thethreshold temperature. In an illustrative embodiment, the substrate isoxidizable silicon and the threshold temperature is the viscoelastict4emperature of silicon dioxide. The resulting oxide has a low defectdensity (D₀), a low interface trap density (N_(it)) and theoxide/substrate interface is planar and substantially stress-free.

[0010] The foregoing has outlined preferred and alternative features ofthe present invention so that those skilled in the art may betterunderstand the detailed description of the invention that follows.Additional features of the invention will be described hereinafter thatform the subject of the claims of the invention. Those skilled in theart should appreciate that they can readily use the disclosed conceptionand specific embodiment as a basis for designing or modifying otherstructures for carrying out the same purposes of the present invention.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The invention is best understood from the following detaileddescription when read with the accompanying drawing figures. It isemphasized that in accordance with standard practice in thesemiconductor industry the various features are not necessarily drawn toscale. In fact, the dimensions of the various features may bearbitrarily increased or decreased for clarity of discussion.

[0012]FIG. 1a is a schematic cross-sectional view of an exemplary MOSstructure according to the present invention;

[0013]FIG. 1b is schematic cross sectional view of an exemplary MOStransistor according to the present invention;

[0014]FIG. 2a is a flow chart of an exemplary fabrication sequence inaccordance with the present invention;

[0015]FIG. 2b is a graph of temperature vs. time in accordance with anexemplary fabrication sequence of the present invention;

[0016] FIGS. 3-5 are schematic cross sectional views illustrating theprocess sequence of forming the oxide layer in accordance with anexemplary embodiment of the present invention;

[0017]FIG. 6 is a transmission electron microscope (TEM) lattice imageof a conventional oxide on a substrate having a conductive layer on theoxide;

[0018]FIG. 7 is a transmission electron microscope (TEM) lattice imageof an oxide layer on a substrate including a conductive layer on theoxide in accordance with an exemplary embodiment of the presentinvention;

[0019]FIG. 8 is a graph of percent degradation of V_(T) (V_(T) drift)over time of illustrative oxides of the present invention and aconventional oxide;

[0020]FIG. 9 is a graph including plots of time vs. substrate current(I_(sub)) indicative of hot carrier aging (HCA) for a conventional oxideand an oxide layer in accordance with an exemplary embodiment of thepresent invention;

[0021]FIG. 10 is a graph including plots of mean time to failure (MTTF)vs. electric field for conventional oxide layers and oxide layers inaccordance with an exemplary embodiment of the present invention;

[0022]FIG. 11 is a comparative graph including plots of transconductance(g_(m)) vs. gate-source voltage (V_(gs)) for 15×15 μm² NMOSFETsincorporating conventional gate oxide layers and those incorporatinggate oxide layers in accordance with an exemplary embodiment of thepresent invention;

[0023]FIG. 12 is a comparative graph including plots of drain currents(I_(d)) vs. drain voltage (V_(d)) for a 15×15 μm² NMOSFETs incorporatingconventional gate oxide layers and those incorporating gate oxide layersin accordance with an exemplary embodiment of the present invention; and

[0024]FIG. 13 is a comparative graph including plots of cumulativeprobability vs. leakage for 15×15 μm² FETS in a n-type tub includingconventional gate oxide layers and gate oxide layers in accordance withan exemplary embodiment of the present invention.

DETAILED DESCRIPTION

[0025] The present invention will now be described more fully withreference to the accompanying drawing figures, in which exemplaryembodiments of the present invention are shown. Referring initially toFIG. 2a, an exemplary sequence for fabricating an oxide layer accordingto the present invention is shown. Step I includes a relatively rapidtemperature increase followed by a more gradual temperature increase.Step I occurs in a dilute oxygen ambient so that very little oxide isgrown in this step. Section II includes a low temperature oxide growthstep. This results in the formation of a first oxide portion over asubstrate at a temperature below a threshold temperature. Step IIIincludes a temperature increase, illustratively in two stages, to atemperature above the threshold temperature. The two stage temperatureincrease is believed to reduce growth induced stress in the oxide. Thistwo stage temperature increase is followed by a high temperature oxidegrowth at a temperature above the threshold temperature. This results inthe formation of a second oxide portion below the first oxide portion.An illustrative cooling step is carried out in step IV. This stepincludes a gradual decrease in the temperature to below the thresholdtemperature, followed by a more rapid temperature decrease. In thiscooling phase, the first oxide portion is believed to act as a sink forstress relaxation.

[0026] A characteristic of the present invention is that the interfacebetween the second oxide portion and the substrate is substantiallyplanar. This planarity is generally measured in terms of surfaceroughness. In the oxide of the present invention the interface has asurface roughness of approximately 0.3 nm or less. Moreover, theinterface between the substrate and the second oxide portion issubstantially stress-free, having on the order of 0 to 2×10⁹ dynes/cm²of compression. This results in a defect density (D₀) on the order of0.1 defects/cm² or less. Finally, the second oxide portion is believedto be a more dense layer of oxide, when compared to conventional oxides.As a result of the dense and substantially stress free characteristicsof the oxide, the interface trap density (N_(it)) of the oxide of thepresent invention is on the order of 5×10¹⁰/cm² to 3×10⁹/cm² or less.

[0027] The resultant ultra-thin oxide having improved planarity, beingsubstantially stress free and being more dense has clear advantages overconventional oxides. These advantages include improvements in bothreliability and performance in devices incorporating the oxide of thepresent invention. To this end, deleterious effects of device parameterdrift, and time dependent dielectric breakdown (TDDB) are reduced byvirtue of the present invention. Moreover, device performance may beimproved through reduced leakage current and increased mobility, forexample. These characteristics of the oxide of the present invention andthe improvements in reliability and performance are discussed more fullyherein.

[0028] Referring to FIG. 1a, an oxide layer 30 in accordance with anexemplary embodiment of the present invention is first described.Illustratively, the oxide layer 30 is incorporated into an integratedcircuit. The oxide layer 30 is disposed over a substrate 22, andincludes a first oxide portion 31 and a second oxide portion 32. Thesecond oxide portion 32 forms an interface 34 with the substrate 22. Thesubstrate 22 illustratively silicon; it may be monocrystalline orpolycrystalline silicon. Most generally it is oxidizable silicon.Illustratively, the oxide layer 30 has a thickness of approximately 40 Åor less. It is anticipated that the thickness of the oxide layer 30 maybe 15 Å-20 Å; and may be even less than 15 Å. Moreover, the oxide layermay have a layer of material 33 disposed between it and a conductivelayer 26. Layer 33 may be a high-k material, including but not limitedto tantalum pentoxide, barium-strontium titanate, and silicatedielectric materials. Additionally, other materials may be disposedbetween the conductive layer 26 and the oxide layer 30 to achieve avariety of results as would be appreciated by the artisan of ordinaryskill.

[0029] The exemplary embodiment of FIG. 1a is generally a MOS structure.Clearly a variety of devices and elements may incorporate thisstructure. These include, but are not limited to a MOS transistor(described below) and a MOS capacitor, a common element in integratedcircuits. Still other devices and elements may incorporate the oxide ofthe present invention, as would be readily apparent to one havingordinary skill in the art to which the present invention relates.

[0030] In the exemplary embodiment shown in FIG. 1b, the oxide layer 30is incorporated into a MOS transistor 21. The MOS transistor includes asource 23 and a drain 24, separated by a channel 25. The transistor mayalso include lightly doped source and drain regions 27 and 28,respectively. The source, drain and channel may be fabricated by avariety of conventional techniques to form a variety of transistorstructures including but not limited to PMOS, NMOS complementary MOS(CMOS) and laterally diffused MOS (LDMOS) devices.

[0031] Turning to FIG. 2b, an illustrative sequence for fabricating theoxide layer 30 by fast thermal processing (FTP) is shown. (Crosssectional views of this exemplary growth sequence and the resultingoxide structure are shown in FIGS. 3-5). Segment 200 indicates a waferboat push step at an initial temperature of approximately 300° C.-700°C., with nitrogen flow of 8.0 L/min and 0.02 to 1% ambient oxygenconcentration. These parameters are chosen to minimize the growth ofnative oxide, which can degrade oxide quality as well as consume theallowed oxide thickness determined by scaling parameters (referred to asoxide thickness budget or scaling budget). Additionally, a load locksystem or a hydrogen bake, well known to one of ordinary skill in theart, can be used to impede the growth of this undesirablelow-temperature oxide.

[0032] Segment 210 is a rapid upward temperature increase atapproximately 50-125° C. per minute to about 750° C.-850° C. This stepis carried out at a very low oxygen ambient concentration (on the orderof 0.05% to 5%) and a high nitrogen ambient. One aspect of the presentembodiment relates to the step of upwardly ramping the temperature at arelatively high rate (segment 210) to minimize the thickness of theoxide formed in this segment (known as the ramp oxide). This helpscontrol the overall thickness of the oxide 30. Thus, through this step,the desired higher growth temperatures (segments 230 and 260) may beattained without sacrificing the oxide thickness budget. Moreover, thisrapid rise in temperature at low ambient oxygen concentrations retardsthe growth of lower temperature oxide, which may be of inferior quality,as discussed above.

[0033] Segment 220 is a more gradual increase in temperature. Segment220 proceeds at approximately 10-25° C. per minute. In the exemplaryembodiment the temperature reached at the end of segment 220 is in therange of approximately 800° C. to 900° C. The same oxygen and nitrogenflows/concentrations used in segment 210 are maintained in segment 220.This control of the ramp up in temperature in segment 220 is alsoimportant as it helps to prevent overshooting the growth temperature ofsegment 230. Finally, the low concentration of oxygen in segment 220selectively retards the growth of oxide during the temperature increaseto a higher growth temperature. Again this helps to preserve the oxidethickness budget.

[0034] Segment 230 is a low temperature oxide (LTO) growth step. In thisstep, the ambient oxygen concentration is about 0.1% to about 10% whilethe ambient nitrogen concentration is 90-99.9%. Dichloroethylene may beadded at 0-0.5% for a time that is dependent upon the desired thicknessas would be appreciated by one of ordinary skill in the art. At the endof segment 230, an anneal in pure nitrogen may be carried out. In theillustrative sequence of FIG. 2, during segments 200-220 an oxide isgrown having a thickness in the range of 5-10 Å. Segment 230 results inthe growth of approximately 2.5-10 Å of oxide. Upon completion ofsegment 230, the growth of the first oxide portion 31 (in FIG. 4) iscompleted. Illustratively, this first oxide portion is grown at atemperature lower than the viscoelastic temperature of silicon dioxide(T_(ve)), which is approximately 925° C. The first oxide portion 31 maycomprise 25-98% of the total thickness of the oxide layer 30. In anexemplary embodiment in which the oxide layer 30 has a thickness of 30 Åor less, the first oxide portion 31 has a thickness of approximately7.5-20 Å. As discussed more fully herein, applicants theorize that thefirst oxide portion 31 acts as a sink for stress relaxation that occursduring the growth of second oxide portion 32 under first oxide portion31.

[0035] Segment 240 is the first segment in the temperature increase to atemperature above the viscoelastic temperature of silicon dioxide. Thisramp up in temperature occurs relatively slowly, at a rate ofapproximately 5-15° C. per minute and in a nearly pure nitrogen ambient(the ambient concentration of oxygen in this segment is illustratively0%-5%). The temperature reached at the end of segment 240 isapproximately 50° C. below the high temperature oxide (HTO) growthtemperature of segment 260. Segment 250 is a modulated heating segmentin which the temperature is increased at a rate of approximately 5-10°C. per minute to a temperature above the viscoelastic temperature. Inthe illustrative embodiment the HTO growth temperature is in the rangeof 925-1100° C. The same flows/concentration of oxygen and nitrogen ofsegment 240 are used in segment 250. At the end of segment 250, the HTOgrowth temperature is reached.

[0036] Segments 240 and 250 are useful steps in the exemplary embodimentof the present invention. As was the case in the temperature ramp-up tosegment 230 the (LTO growth segment) the careful ramp-up of temperaturein segments 240 and 250 prevents overshooting the desired growthtemperature, in this case the HTO growth temperature of the presentinvention. The rate of temperature increase at the illustrated lowambient oxygen concentration is useful in retarding oxide growth therebypreserving the oxide thickness budget. Finally, applicants believe thatthe careful heating in a low oxygen ambient in segments 240 and 250reduces growth stress, and consequently a reduces the occurrence ofoxide growth defects (e.g., slip dislocations and stacking faults).

[0037] Segment 260 is the HTO growth step, where the growth temperatureis illustratively above the viscoelastic temperature of silicon dioxide.The temperature achieved at the end of segment 250 is maintained in thegrowth step in segment 260 in a 25% or less oxygen ambient forapproximately 2 to 20 minutes so that an additional 2-12 Å of oxide maybe grown at high temperature. The second portion may comprise on theorder of 2-75% of the total thickness of the oxide layer 30. The finalportion of segment 260 may include an anneal in pure nitrogen.Applicants believe (again without wishing to be bound to such a belief)that the high temperature growth above the viscoelastic temperature(approximately 925° C.) results in the growth of an oxide (second oxideportion 32) having certain properties.

[0038] Segment 270 of the exemplary embodiment of FIG. 2 is a coolingsegment also referred to as a modulated cooling segment. A temperatureramp down is carried out at a rate of approximately 2-5° C. per minuteto a temperature at the end of segment 270 which is below theviscoelastic temperature. For example, the temperature reached at theend of segment 270 is in the range of 900-800° C. Segment 270 is carriedout in a nearly pure nitrogen ambient, which is inert. During thecooling of a grown oxide to below the viscoelastic temperature, stressmay result in the oxide, particularly at the substrate-oxide interface.As a result of this stress, defects such as slip dislocations andoxidation induced stacking faults may be formed at energetically favoredsites such as heterogenities and asperities. These defects may be viewedas routes for diffusional mass transport and leakage current paths whichcan have a deleterious impact on reliability and device performance. Themodulated cooling segment, and the stress absorbing or stress sinkcharacteristics of the first oxide portion 31 (particularly during themodulated cooling segment) results in a substantially stress freeoxide-substrate interface. Moreover, the defect density is reduced.Finally, segment 280 represents a further ramp down at a faster rate onthe order of approximately 35-65° C. per minute in an inert ambient suchas pure nitrogen. Segment 290 is the boat pull at about 500° C. in apure nitrogen ambient.

[0039] FIGS. 3-5 show the cross sectional view of the steps of formingthe oxide 30. The substrate 22 is generally oxidizable, illustrativelymonocrystalline or polycrystalline silicon, or silicon islands insilicon on insulator (SOI) substrates. The first oxide portion 31 may beconsidered the low temperature oxide (LTO) portion, having been formedbelow approximately 925° C. In addition to providing a stress sinkduring the formation of the second oxide portion 32 the first oxideportion 31 enables oxide growth thereunder. As such, first oxide portion31 must allow the diffusion of oxygen there through so that oxidation ofthe substrate 22 can occur, resulting in the second oxide portion 32. Inthe illustrative embodiment, the first portion is silicon dioxide.However, other materials may be used in this capacity as well.Alternative materials include but are not limited to a lightly nitrided(for example 0.2 to 3% nitrogen by weight) silicon dioxide layer so thatboron penetration is prevented, which is beneficial in the prevention ofpoly-depletion. Moreover, the first oxide portion 31 may be steam oxideor a grown-deposited composite oxide layer. The second oxide portion 32may be considered the high temperature oxide (HTO) portion grown at atemperature below the viscoelastic temperature of 925° C. For purposesof illustration, the high temperature growth of the second portion 32 isin the range 925° C.-1100° C.

[0040] Characteristics of the oxide layer 30 of the present inventioninclude improved interfacial planarity and a reduction in the stressboth in the bulk of the oxide and at the interface between the oxide andthe substrate. This become readily apparent from a comparison of theFIGS. 6 and 7.

[0041]FIG. 6 is a TEM lattice image of a MOS structure incorporatingconventional oxide; FIG. 7 is a TEM lattice image a MOS structureincorporating the exemplary oxide of the present invention. FIG. 6 showsa substrate 62, a conventional oxide layer 60 and a conductive layer 66.In the image of FIG. 6, there is a stress band 63 (dark contrast)indicating the existence of a strain field between the oxide 60 and thesubstrate 62. In addition, the interface between the oxide 60 and thesubstrate 62 is relatively rough (i.e. not planar). Conventional oxidesexhibit a surface roughness on the order of 5 Å or greater. Among otherdrawbacks, this degree of roughness can result in carrier scattering inthe channel of an exemplary MOS transistor, resulting in reduced carriermobility.

[0042] In contrast to the conventional oxide in FIG. 6, the interfacebetween the graded grown oxide 30 and the substrate 22 in the exemplaryembodiment of the present invention shown in FIG. 7 shows no darkcontrast in the TEM image. Therefore, there is no noticeable stressband. Instead, the interface between the graded grown oxide 30 and thesubstrate 22 in the illustrative embodiment is substantially stressfree. Moreover, the interface is substantially planar without anyobservable breakage in the Si (111) lines near the interface. Usingstandard stress measurement techniques such as x-ray micro-diffractiontechniques, the silicon (400) Bragg peak profile indicates 2×10⁹dynes/cm² of compression measured by similar technique. Finally, theinterface between the oxide 30 and the substrate 22 is substantiallyplanar having a planarity that is not detectable within the resolutionof conventional TEM imaging devices (approximately 3 Å).

[0043] As alluded to above, by virtue of the substantially stress freeand planar Si—SiO₂ interface and the denser second oxide portion 32formed by the present invention oxide of the present invention, thereare improvements in the reliability of devices employing the oxide ofthe present invention. The device parameter drift during normaloperation is often more significant than oxide breakdown when evaluatingthe reliability device employing the thin gate oxide. Device parameterdrift can cause a device to fail the required parameter specificationslong before an oxide breakdown event occurs. Drift in devices isdominated by two mechanisms. In a p-MOS device, bias-temperature (BT)drift is the dominant factor, while in an n-MOS device hot carrierdegradation (also referred to as hot carrier aging (HCA)) dominates.

[0044] The migration to surface channel devices for better off-stateleakage performance can result in drift in the threshold voltage (V_(T))under bias temperature (BT) conditions. This drift phenomenon isattributed to the creation of hot holes due to impact ionization byelectrons which have tunneled into the silicon substrate. These hotholes are trapped within the oxide. It is theorized that the trapswithin the oxide are due to weak Si—O bonds in the bulk oxide whichbehave like hole traps. These trapped holes act as positive chargewithin the oxide which behave like hole traps. These trapped holes actas positive charge within the oxide resulting in shift in the thresholdvoltage (V_(T)). In contrast to conventional oxides, the second oxideportion 32 of the present invention is believed to have a reduced numberof weak silicon-oxygen bonds. Accordingly, there is a reduced incidenceof traps. Again, this follows from the substantially stress free, densenature of the second oxide portion 32. The propensity for thresholdvoltage shift in the oxide of the present invention is significantlylower. This is shown in FIG. 8, where the percentage degradation ofthreshold voltage in two illustrative samples of the oxide of thepresent invention having thicknesses of 36 Å (plot 81) and 32 Å (plot82) is compared to a conventional oxide having a thickness of 33 Å (plot83). As is clear form FIG. 8, bias temperature (BT) drift issignificantly lower in devices using the oxide of the present invention.

[0045] Another phenomenon that can adversely impact the reliability of adevice is hot carrier aging (HCA). In sub-micron gate structures, hotcarrier effects result from a increased lateral electric field in thereduced length channel. This causes inversion-layer charges to beaccelerated (or heated) to an extent that they may cause a number ofharmful device phenomena, commonly referred to as hot carrier effects.An important hot carrier effect from the standpoint of reliability indevices is the damage inflicted on the gate oxide and/or thesilicon-silicon dioxide interface by hot carriers. Hot carrier aging isbelieved to be due to interface trap generation or the breaking ofpassivating dangling bonds. To this end, dangling bonds in thesilicon-silicon dioxide interface are conventionally passivated in ahydrogen ambient, thereby reducing the number of interface traps. Whilethis passivation technique has met with some success in conventionaloxides, hot carriers can readily break silicon-hydrogen bonds, therebyre-establishing the previously passivated interface traps. The traps inthe interface act as scattering centers, thereby reducing the mobilityof carriers within the channel. As is known, the drive current, I_(on)(or saturation current, I_(dsat)), and the transconductance g_(m) aredirectly proportional to the mobility of the carriers in the channel.Accordingly, as the scattering centers become more abundant due to hotcarrier effects, mobility of carriers in the channel is reduced, and thedrive current and transconductance are reduced. Thus, the number ofinterface traps can cause the device to degrade (age) due to drift indevice parameters such as drive current and transconductance. Thisdegradation has a deleterious impact on device reliability.

[0046] The oxide of the present invention has a reduced incidence ofdangling silicon bonds, and thereby a reduced number of interface traps.Applicants theorize that this is a result of a more complete oxidationprocess and because the interface is substantially stress-free andplanar. Moreover, since there are fewer interface traps in the oxide ofthe present invention, there are fewer traps passivated with hydrogen;and it is anticipated that there will be less device drift due tohydrogen release in devices which incorporate the oxide of the presentinvention.

[0047] Measured by standard technique, the interface trap density(N_(it)) of the oxide of the present invention is on the order of3×10⁹/cm² to 5×10¹⁰/cm² or less. The resulting improvement in hotcarrier aging can be seen clearly in the graphical representation ofFIG. 9. The hot carrier aging criteria by convention is a 15% change intransconductance. The plot labeled 90 is for a device incorporating a 32Å oxide layer fabricated in accordance with the present invention. Theplot labeled 91 is for a device incorporating for a conventional oxideof the same thickness. For example, the substrate current limit of 3μA/μm is achieved at 120 hours in a conventional oxide in a MOSFET; inan exemplary oxide of the present invention this is limit achieved at400 hours. As will be readily appreciated of those of ordinary skill inthe art, hot carrier aging is improved by a factor of 3-10 by the oxideof the present invention when compared to conventional oxides.

[0048] The oxide of the present invention also results in an improvementin the time dependent dielectric breakdown (TDDB), another measure ofreliability of the MOS device. This improvement in TDDB is believed tobe a direct result of the stress free and high quality silicon-silicondioxide interface of the present invention. As discussed above, due tothe planar and substantially stress free interface between the substrateand oxide, the defect density D₀ is lower. As a result, it is believedthat there are fewer defects, which can lead to diffusional masstransport and leakage current. Ultimately this can lead to animprovement in charge fluence or charge-to-breakdown (Q_(db)) anddielectric breakdown under temperature (for example >150° C. to 210° C.)and field acceleration (for example 3-6 MV/cm).

[0049] As shown in FIG. 10 the oxide of the present invention results ina factor of 8-10 improvement of TDDB when compared to conventionaloxides. In particular the mean time to failure (MTTF) vs. electric fieldstrength is plotted for various conventional oxides and an exemplaryoxide of the present invention in a 0.25 microns CMOS device. The plot100 is for an illustrative oxide of the present invention having athickness of 32 Å, while the corresponding conventional oxides of thesame thickness are represented by plots 102 and 103. For purposes ofillustration in an exemplary device, the oxide of the present inventionexhibits a breakdown at 10⁵ sec at a field of 5.5 MV/cm, compared to theconventional oxide which exhibits a breakdown at approximately 2×10⁴ secat the same electric field. Plot 101 is for an illustrative oxide of thepresent invention having a thickness of 28 Å, while that of plot 104 isfor a 28 Å thick layer of conventional oxide. As can be seen, theillustrative oxide of the present invention exhibits a breakdown atabout 2×10⁴ sec for a 5.5 MV/cm electric field compared to a breakdownat 7×10³ sec for the same electric field for a conventional oxide.

[0050] As stated previously, device performance is also improved byvirtue of the oxide of the present invention. As discussed above, thecarrier mobility within the channel can be significantly impacted by thenumber of traps and the degree of surface roughness (planarity) at theoxide-substrate interface. A more planar (less rough) interface and areduction in the number of traps is manifest in an improvement inmobility. This results in an improvement in transconductance. This canbe seen most readily from a review of FIG. 11. The even number plots110, 112, 114, 116 and 118, show the transconductance vs. gate-sourcevoltage in an illustrative device using the oxide of the presentinvention. The odd number plots (111, 113, 115, 117 and 119) are plotsof transconductance vs. gate-source voltage in devices usingconventional gate oxides. The transconductance vs. gate-source voltage(V_(gs)) are plotted for a 15×15 μm² NMOSFET. Plots 110 and 111 are fora drain voltage of 2.1 volts. Plots 112 and 113 are for a drain voltageof 1.6 volts, while plots 114 and 115 are for a drain voltage of 1.1volts. Plots 116 and 117 are for a drain voltage of 0.6 volts and plots118 and 119 are for a drain voltage of 0.1 volt. As would be appreciatedby one of ordinary skill in the art, FIG. 11 shows the oxide inaccordance with exemplary embodiment of the present invention provides a5-6% increase in channel mobility. This results in an improvement ofdrive current (saturation current I_(dsat)) on the order of 20% in theillustrative embodiment.

[0051] Turning to FIG. 12, a comparative result of the oxide of thepresent invention and conventional oxides for a drive current for a15×15 μm² NMOSFET is shown. The drain current is plotted vs. drainvoltage for a series of gate voltages. Plots 120 and 121 are for gatevoltages of 2.5 volts for the oxide layer of the present invention and aconventional oxide, respectively. Plots 122 and 123 are for a gatevoltage of 0.2 voltages for the oxide of the present invention and aconventional oxide, respectively. Finally, plots 124 and 125 are for agate voltage of 1.5 volts for the oxide of the present invention and aconventional oxide, respectively. As can be appreciated by one havingordinary skill in the art, devices incorporating the oxide of thepresent invention show improved sub-threshold and saturationcharacteristics compared to devices using conventional oxides.

[0052] Leakage current characteristics for a transistor employing theoxide of the present invention are also improved. As discussed above,leakage current is believed to be attributable to oxide defects (D_(o))The oxide of the present invention has a defect density of 0.1defects/cm² or less. Again, for thin gate dielectrics, the majorcontributors to D₀ are the growth induced defect density and theintrinsic stress within the oxide layer. The defects are formed atenergetically favored sites such as heterogenities and asperities. Thesedefects tend to grow outwardly as oxidation consumes silicon around thedefect and eventually a network of defects may exist. These defects maybe viewed as pipes for diffusional mass transport as well as potentialleakage current paths, which can have a significant impact on devicereliability and performance.

[0053]FIG. 13 is a graph of cumulative probability vs. leakage currentfor gate oxides in an n-type tub at a voltage 2.0 volts. Plot 130 is fora gate oxide layer in accordance with the present invention having athickness of 28 Å, while plot 131 is for a conventional oxide of thesame thickness. Plot 132 is for an oxide layer of the invention of thepresent disclosure having a thickness of 32 Å, while plot 133 is for aconventional oxide having a thickness of 32 Å.

[0054]FIG. 14 presents various leakage plots for a p-type tub at avoltage of 2.0 volts. Plot 134 is for a gate oxide in accordance withthe present invention having a thickness of 28 Å, and plot 135 is for aconventional oxide of the same thickness. Plot 136 is for an oxide ofinvention of the present disclosure having a thickness of 32 Å, whileplot 137 is for a conventional oxide layer having a thickness of 32 Å.From FIGS. 13 and 14 it can be appreciated that the oxide of the presentinvention offers a 8-10 times improvement leakage current. Moreover,with this significant improvement in leakage current, as one of ordinaryskill in the art would readily appreciate, the charge control over thechannel is improved, with improved sub-threshold characteristics(I_(off)).

[0055] Although the present invention has been described in detail,those skilled in the art should understand that they can make variouschanges, substitutions and alterations herein without departing from thespirit and scope of the invention in its broadest form.

What is claimed is:
 1. A process for fabricating an oxide, the processcomprising: (a) exposing said substrate to a first oxidizing ambient,wherein exposing said substrate to a first oxidizing ambient includesincreasing from an initial temperature to a first temperature below athreshold temperature at a first ramp rate, increasing from said firsttemperature to a second temperature below said threshold temperature ata second ramp rate, and growing at least a portion of said oxide; (b)exposing said substrate to a second oxidizing ambient, wherein exposingsaid substrate to a second oxidizing ambient includes increasing fromsaid second temperature to a third temperature at a third ramp rate, andincreasing from said third temperature to a temperature above saidthreshold temperature at a fourth ramp rate; and (c) cooling saidsubstrate to a temperature below said threshold temperature, whereinsaid oxide has a thickness of 40 Å or less.
 2. The process as recited inclaim 1, wherein said first temperature below said threshold temperatureis in the range of 750° C. to 850° C. and said first ramp rate isapproximately 50° C.-125° C. per minute.
 3. The process as recited inclaim 1, wherein said second temperature below said thresholdtemperature is approximately 800° C.-900° C. and said second ramp rateis approximately 10° C.-25° C. per minute.
 4. The process as recited inclaim 1, wherein step (b) further comprises: increasing from said secondtemperature to said third temperature at a ramp rate of approximately5-15° C./minute in an ambient oxygen concentration of approximately0%-5%; increasing from said third temperature to said temperature abovesaid threshold temperature at a ramp rate of 5-10° C./minute in anambient oxygen concentration of approximately 0%-5%; and growing atleast a portion of the oxide in an oxygen ambient concentration of about25% or less.
 5. The process as recited in claim 1, wherein step (c)further comprises: reducing from said temperature above said thresholdtemperature to approximately 800° C. to 900° C. at a rate of about 2°C./min-5° C./min; and reducing said temperature of approximately 800° C.to 900° C. to a boat pull temperature at a rate of about 35° C./min-65°C./min, wherein said oxide portion formed in step (a) is a first oxideportion and acts as a stress sink to a second oxide portion formed instep (b) during at least a portion of said cooling.
 6. The process asrecited in claim 1, wherein said substrate is oxidizable silicon andsaid threshold temperature is the viscoelastic temperature of silicondioxide.
 7. The process as recited in claim 1, wherein said substrate isoxidizable.
 8. The process as recited in claim 1, wherein said substrateis chosen from the group consisting essentially of monocrystallinesilicon, polycrystalline silicon and silicon islands in a silicon oninsulation (SOI) substrate.
 9. The process as recited in claim 1,wherein said threshold temperature is the viscoelastic temperature ofSiO₂.
 10. The process as recited in claim 5, wherein said thresholdtemperature is the viscoelastic.